Which of the following processor architecture supports easier instruction pipelinin

1.An integer variable with value 255 is stored in memory location at 0x8000. The processor word length is 8 bits and the processor is a big endian processor. The size of integer is considered as 4 bytes in the system. What is the value held by the memory location 0x8000?


(a) 0xFF (b) 0x00 (c) 0x01 (d) None of these4. The instruction set of RISC processor is

(a) Simple and lesser in number (b) Complex and lesser in number

(c) Simple and larger in number (d) Complex and larger in number

2. Which of the following is true about CISC processors?

(a) The instruction set is non-orthogonal

(b) The number of general purpose registers is limited

(c) Instructions are like macros in C language

(d) Variable length Instructions

(e) All of these

(f) None of these

3. Which of the following processor architecture supports easier instruction pipelining?

(a) Harvard (b) Von Neumann

(c) Both of them (d) None of these

4. Microprocessors/controllers based on the Harvard architecture will have separate data bus and instruction bus. This allows the data transfer and program fetching to occur simultaneously on both buses. State True or False

(a) True (b) False

find the cost of your paper

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