What is the maximum ISR size allocated for each interrupt in the standard 8051 Architecture

1. Which port of 8051 is ‘true-bidirectional’?


(a) Port 0 (b) Port 1 (c) Port 2 (d) Port 3

2. For confi guring a port pin as input port, the corresponding port pins bit latch should be at

(a) Logic 0 (b) Logic 1

3. Port 2 latch contains A5H. What will be the value of Port 2 latch after executing the following





(a) 00H (b) 0FH (c) A5H (d) FFH3

4. The alternate I/O function for the pins of Port 3 will come into action only when the corresponding bit latch is

(a) 1 (b) 0

5. The interrupts Timer 0 and serial interrupt are enabled individually in the interrupt enable register and high priority is given to Timer 0 interrupt by setting the Timer 0 priority selector in the interrupt priority register.

It is observed that the serial interrupt is not at all occurring. What could be the reasons for this?

(a) The global interrupt enable bit (EA) is not in the set state

(b) The Serial interrupt always occurs with Timer 0 interrupt

(c) There is no Serial data transmission or reception activity happening in the system

(d) None of these (e) (a) or (b) or (c)

6. Timer 0 and External 0 interrupts are enabled in the system and are given a priority of 1. Incidentally, the Timer 0 interrupt and External 0 interrupt occurred simultaneously. Which interrupt will be serviced by the 8051 CPU?

(a) Timer 0 (b) External 0

(c) External 0 interrupt is serviced fi rst and after completing it Timer 0 interrupt is serviced

(d) None of them are serviced

7. What is the maximum ISR size allocated for each interrupt in the standard 8051 Architecture

(a) 1 Byte (b) 4 Byte (c) 8 Byte (d) 16 Byte


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